Power amplifiers (PAs) are commonly used in wireless devices to amplify a signal for transmission. PAs are typically formed of multiple stages, and often include a final gain stage, commonly referred to as an output gain stage, to amplify the signal to a desired power level for its output to a load such as an antenna that radiates the amplified signal.
Wireless communication systems dictate the amount of power to be output. Different requirements may exist in different communication protocols. Many communication systems have various requirements for a handset to achieve with relation to power, efficiency, and linearity over varying signal levels. For example, a variety of communication systems, including enhanced data rates for GSM evolution (EDGE), long term evolution (LTE/4 G), WiFi in accordance with an IEEE 802.11 standard, worldwide interoperability for microwave access (WiMax), code division multiple access (CDMA), and wideband-code division multiple access (W-CDMA) all have varying requests. For example, a W-CDMA band 1 (B1) PA should be able to output approximately 30 dBm of power at an efficiency better than 40% and at a linearity of better than −40 dBc of adjacent channel leakage ratio (ACLR).
Many of the mainstream linear PAs today utilize bipolar transistors in fabrication processes such as a gallium arsenide (GaAs) process which offers high unity-current-gain frequency (ft) gain devices (bipolar transistors). However, other PAs implement the PA using a complementary metal oxide semiconductor (CMOS) process. In such systems, the output gain stage typically formed of CMOS devices, including both NMOS and PMOS output transistors. In CMOS processes, a PMOS device is typically slower (lower ft) than the corresponding NMOS device, and hence, is much larger than a corresponding (i.e., same relative transconductance) NMOS device, e.g., approximately 2-3× larger. Such larger PMOS transistors are needed to form a true complementary gain-stage to meet the requirements of different protocols. As a result, a significant amount of area is consumed by the PMOS devices and a correspondingly large parasitic capacitance is created. In turn, this requires a relatively small inductance to resonate out this capacitance, which can be difficult to fabricate. Furthermore, the larger PMOS devices present a larger non-linear gate capacitance that can adversely affect linearity of the PA.